1. Field of the Invention
The invention relates to local clock generation. More particularly, the invention relates to the generation of an accurate clock with a low jitter in a chip, for example the chip of a smartcard supporting USB standard (Universal Serial Bus is defined by a set of specifications published by the USB Implementer Forum). But the invention can be applied to any chip that needs an accurate clock with a low jitter, which clock is recovered from a received stream of data.
2. Description of the Related Art
According to USB standard, any USB device, root hub, hub or peripheral, needs to comprise a clock generation circuit providing an accurate clock signal. The accurate clock signal is required for receiving and sending data. For portable devices like smartcards or Flash cards supporting USB, it is preferable to have an on-chip clock generation circuit.
Several problems occur when implementing such an accurate clock generation circuit inside an Integrated Circuit (IC) into a portable device. The problems are due to the fact that IC technology itself is not very accurate for clock generation. Commonly, without correction the timing precision is around 30%. There are also some constraints regarding the power consumption that has to be as low as possible.
Several solutions of clock generation are known for auto-calibrating an internal clock generation circuit using the received data stream. U.S. Pat. No. 6,343,364 ('364) discloses a circuit comprising a free-running high frequency oscillator coupled to a counter used as a programmable timing synthesizer in relation with the received data stream. In '364, the circuit is self-calibrated by counting the number of free-running oscillator cycles in a period of time corresponding to one or more bits of an USB downstream signal. The number of cycles is then used for programming an accurate clock synthesizer. This solution is well adapted for USB low-speed communication wherein a frequency accuracy of 1.5% is required.
U.S. patent application No. 2004/0148539 ('539) discloses an improvement for adapting '364 knowledge to USB full-speed communication. The improvement consists in using bit-patterns, called Start Of Frame (SOF), broadcasted periodically by the host to all full-speed devices. SOF time intervals have a precision higher than the bit rate precision.
In addition to the frequency accuracy, there is the need to minimize power consumption. Both '364 and '539 use a ring oscillator that provides a plurality of phase signals that provide the Step of Time equal to the period of the ring oscillator divided by the number of phase signals. The multi-phase oscillator can provide the same Step of Time as a conventional oscillator but it runs at a lower frequency and thus minimizes power consumption. Also, the oscillator enables a longer period of time to use larger capacitors and reduces parasitic effects partially responsible for the jitter.
In view of this prior art a problem still remains. In the worst case of the full-speed USB standard, the jitter should be reduced to ±1.5 ns on the transmitted data stream. To achieve this jitter tolerance on the data stream, a required tolerance on the jitter is 210 ps for the oscillator providing the USB clock signal. According to prior art, the Step of Time should be lower than the required jitter on the oscillator. This requirement needs to use a very high frequency in combination with a high number of phases and results in an important power consumption. Another solution is required for reducing the power consumption.